FET

There is a figure in the application note showing a resistor inserted at the MOS FET gate, but I'm not sure how to select the resistance value of this resistor (it seems to differ depending on the product).
The MOS FET operates on voltage, so I feel that this resistor is not necessary.
Why is it there?

Amongst other things, the FET gate resistor is inserted to:

- protect against parasitic oscillation, - protect against surge on the gate, - suppress the switching speed, - make adjustments to match the current drive capacity of the previous stage.

The main purpose of this resistor is to protect against parasitic oscillation (resonance).
Parasitic resonance occurs when Q of the resonant circuit becomes large due to parasitic capacitance and parasitic inductance in the MOS FET.
Therefore by adding a several-10 to several-100 Ω resistor to the gate, the Q value is lowered and oscillation and ringing are reduced.

A resistor with an even higher resistance value is necessary to protect against surge, but be aware that a high resistance causes the operation speed to drop significantly.
We therefore advise you to determine an appropriate resistance value that accords with the specifications of your system.

Is FET gate protection required?

The protection diode embedded between the FET gate and the source serves to protect against electrostatic damage during handling.
If there is a risk of the rated voltage being exceeded in the circuit that is actually used, insert a gate protection circuit such as a constant voltage diode.

Caution

The characte s of the RF & microwave devices may degrade if a diode for gate protection is connected.

(2007/04)

Show me an example, if there is one, of using an external constant-voltage diode to protect power MOSFET 2SK1288 from damage due to static electricity.

The figure of a general application example, though not one of using the 2SK1288, is shown below.
The absolute maximum rating V_GSS of the 2SK1288 is 20 V, so set a constant-voltage diode such that V_GS does not exceed 16 V for protecting the gate. (Being 80% of the absolute maximum rating is assumed. The recommended value with margin is about 10 V.)

(2008/02)

What are the specifications of the cut-off currents such as I_DSS and I_GSS?

These are leakage currents that flow between the respective pins when the gate of the MOSFET is in an off state.
I_DSS is a drain-source cut-off current. It is the leakage current between the drain and source at V_GS = 0.
This current is defined by applying the maximum rating V_DSS between the drain and source.



I_GSS is a gate-source cut-off current. It is the leakage current between the gate and source at V_DS = 0 and is defined by applying the maximum rating V_GSS between the gate and source.

(2008/02)

What is the maximum rating of the internal diode between the drain and the source?

There is no rating for the internal diode by itself.
The forward current and withstand voltage are as listed in the absolute maximum ratings.

Can the parasite diode between the drain and the source be used as a flywheel diode?

The parasite diode is not suitable for high-speed control due to a long reverse recovery time, so such use of the parasite diode should be refrained from.

In the absolute maximum rating between the gate and the source of the 2SK3062, etc., why are the AC rating and the DC rating different? AC: ± 20 V, DC: +20 V, -10 V

In the case of AC, the gate charge is repeatedly charged and discharged. Therefore, compared to DC, the gate is subject to less stress. Based on this fact, the ratings are given separately for AC and DC.

How are V_DSS and V_GSS defined?

V_DSS is the maximum voltage that can be applied between the drain and source while the gate and source are short-circuited.



V_GSS is the maximum voltage that can be applied between the gate and source while the drain and source are short-circuited.



For how to read the symbols, see How to read symbols of absolute maximum ratings.

(2008/02)

Why is the total dissipation (P_T) of a MOS FET considerably smaller than the value of "drain-source voltage V_DSS" x "drain current I_D"?

Drain-source voltage V_DSS is the withstand voltage in the OFF state (V_GS = 0 V), not the driven voltage in the ON state.
Since the ON resistance is small, a large current flows, and the MOS FET cannot drive such a high voltage. If drain current I_D exceeds the absolute maximum rating, please take measures such as attaching a limiting resistor.

(2008/01)

What is the value of the thermal resistance between the junction and drain pin in the 2SK3061 ?

I'll answer this question substituting "case" for "drain pin".
The thermal resistance between the channel and case (Rth(ch-c)) is calculated by the following expression:


Therefore the thermal resistance between the channel and case in the 2SK3061 is:

Only the transient thermal resistance of Rth (ch-a) is described in the data sheets of 8-pin SOP products such as the uPA1764; is there no data available for the transient thermal resistance of Rth (ch-c)?

The channel-to-case thermal resistance (Rth (ch-c)) is only prescribed for packages with a structure in which a heat sink is used.
8-pin SOP products such as the uPA1764 do not have a structure in which a heat sink is used, so the channel-to-case thermal resistance (Rth (ch-c)) is not prescribed.

Is it OK to consider that the voltage at which a FET switches on (D-S on) is equal to the gate cutoff voltage (VGS (off)) ?

No. The gate voltage depends on the level to which you set the current that flows between D and S of the FET. Therefore, the on-voltage needs to be determined by the customer.
Further, the gate cutoff voltage (VGS (off)) is the voltage at which the FET switches off (D-S off).

Are the switching characteristics the same even if a current flows between the source and drain of an FET in the reverse direction?

No. The FET has a body diode between its source and drain, so the current flowing in the reverse direction is the forward current of the diode. Consequently, the current flows through the diode when the ON resistance of the FET is high, and the FET cannot perform its switching operation.

(2008/04)

Can the current be pushed from the N-channel MOSFET source toward the drain, in order to use the MOSFET as a rectifier diode?
Also, can this method be used as a general usage method for all MOSFETs?

This usage is a general usage method for all MOSFETs.
However, since it does not constitute design that takes into consideration other factors such as trr in particular, if the proposed application requires characteristics of special diodes such as SBD/FRD (Note) (short trr, etc.), it is necessary to use standalone diodes such as SBD, FRD, etc.
Note: SBD Schottky Barrier Diode, FRD Fast Recovery Diode

A bridge control circuit for a motor can be cited as an example where a diode is used for rectification. In this case, the pulse width is controlled by PWM. When all the FETs are off, a regenerative current flows from the ground to the power supply via a body diode because of a potential difference that is generated by the motor, which continues revolving due to inertia.

(2008/04)

If pushing the current from the source toward the drain, can the allowable power dissipation, on-resistor, etc., be interpreted to be the same as the data sheet values?

The power ratings are the same as those for the forward direction. Regarding the on-resistor, no ratings are provided as electrical characteristics.
Based on the element structure, if gate forward voltage is applied, the structure is such that the parasite diode and the on-resistor of the MOS are connected in parallel.
If voltage drops caused by the on-resistor of the MOS are considerably lower than VF, almost no current flows to the diode and instead it flows to the on-resistor.

Can the higher pulse current be flown into FET if the pulse width of the condition (10 us) decreases (e.g., several ns)?

The pulse current rating will not changed even if the pulse width changes. The pulse current rating is uniquely determined under conditions PW ≤ 10 us, duty cycle ≤ 10%, and this must not be exceeded even if the pulse width is in the order of several ns. The slant line of each pulse width shown in the safe operation area indicates an area that is restricted by the power rating.

According to the data sheet of the 2K2857, the maximum rating of the drain current (DC) is ±4 A. The FET will be used with a pulse waveform instead of DC.
If a pulse waveform with a period of 1 ms and a duty factor of 45% is used, how much current is allowed to flow through the FET in terms of effective value?

The actual value in the current rating is not defined.
Even if the duty factor is 45% as mentioned in your question, apply a drain current (DC) rating of ±4 A.

(2007/08)

R_DS(on)Limited is indicated by dotted lines on the graph that shows the safe operating area in the forward direction of a power MOS FET. What kind of limitation is this?

The R_DS(on)Limited dotted line shows the limits of the area in which characteristics cannot be obtained due to ON resistance.
In other words, the lower the V_DS (drain-to-source voltage) becomes, the more I_D (drain current) is limited by ON resistance.

(2006/04)

I would like to ask about a MOS FET's Qg, Qgs, and Qgd parameters.

For example, in the case of the 2SK3510, the data sheet states the following:
Qg = Typ. 150 nC
Qgs = Typ. 30 nC
Qgd = Typ. 52 nC

Why is this not Qg = Qgs + Qgd?

Please look at the following DYNAMIC INPUT/OUTPUT CHARACTERISTICS graph from the 2SK3510 data sheet.



Qgs indicates the charge until the FET enters the ON state.
The capacitor between the gate and the source charges until the FET enters the ON state.
In the graph, the initial ramp-up period of V_GS is equivalent to this state.
From the graph, this figure equates to about 30 nC.

Qgd indicates the charge from when the FET enters the ON state to when the voltage between the drain and source starts to drop. In this period, the capacitor between the gate and the drain is being charged. In the graph, the period of flat V_GS after initial V_GS ramp-up is equivalent to this state.
From the graph, this figure in this flattening out period equates to about 50 nC.

Once the capacitor between the gate and the drain is charged, the gate voltage ramps up again.
As described in the specification conditions, Qg indicates the total gate charge required to obtain a gate-to-source voltage of 10 V.
In other words,Qg = Qgs + Qgd + (Charge necessary for V_GS to reach 10 V during ramp up after flattening).
However, from the graph, this figure equates to about 150 nC when V_DD = 60 V.

For this reason, Qg in the actual specifications does not equal Qgs + Qgd.

(2006/10)

To what is the rear heat spreader fin of the uPA2700TP (8-pin SOP) connected?

It is connected to the drain, as shown in the package drawing in the data sheet.

(2006/10)

I want to design a power supply ON/OFF circuit using the 2SK1583.
Specifically, I'm thinking to connect the power supply source to the drain side, use the source side as the power supply for the entire board, and to switch the power supply to the board on and off by switching the gate pin between high and low. Is this possible?

The circuit you are thinking of is most likely a high-side switch that uses an FET.
When developing a high-side switch, you would normally use a P-channel device (2SJ) and supply the power from the source side to the drain side. This is because, when using an N-channel FET (2SK), as shown in Figure 1, the voltage between the gate and the source fluctuates due to the voltage supplied from the drain side to the source side when the transistor is ON, causing unstable operation.
A complex circuit configuration would therefore be necessary to prevent this.
However, when using a P-channel FET, as shown in Figure 2, the voltage between the gate and the source is fixed, so stable operation can be achieved with a much simpler circuit configuration.

(2007/01)

The data sheet describes derating factor dT (%) for the case temperature as shown in the figure below.
Does this derating factor also apply to the drain current (direct current), or any other parameters?

The derating factor does not apply to the drain current, but as the temperature rises, the internal resistance becomes higher, and as a result, the drain current is affected by the derating factor in the form of power dissipation.
The drain-source voltage is not affected by the derating factor, but usage within 80% of the rating is still advised.

(2007/02)

As a result of measuring, the 2SJ601-Z gate cut-off voltage differs from the electrical characteristic listed in the data sheet. Why?

The 2SJ601-Z gate cut-off voltage characteristics described in the data sheet is specified as the gate voltage under the off conditions of V_DS=-10 V and I_D=-1 mA.
If the off conditions, measurement temperature, etc., differ from our conditions, the gate cut-off voltage is different from the value listed in the data sheet.
Please check the conditions again.

(2007/03)

The uPA2755 is a product with 2 elements, but is the absolute maximum rating of drain current of 8 A the total for the two elements?

No. The absolute maximum rating of drain current of 8 A is the rating for just one element.
In the case of two elements, the absolute maximum rating of drain current is restricted by the total dissipation.

(2007/10)